Conventional semiconductor memory devices utilizing multiple array memory structures, such as synchronous dynamic random access memory (SDRAM) devices and pseudo-static random access memory (PSRAM) devices employing bank architecture, generally employ some type of row redundancy scheme. Row redundancy involves replacing defective wordlines, or rows of memory cells, with non-defective wordlines. A wordline can be defective for many reasons including short circuits to bitlines or bad transistors or storage capacitors in the associated memory cells.
When a defective row is replaced, it is not physically replaced, but logically replaced. Typical row redundancy schemes compare a received row address to address of known defective rows. If the comparison produces a match, a replacement, or redundant, row is fired in place of the defective “normal” row. In a memory device employing a bank structure, the location of the replacement row is not restricted to the array containing the defective row, and the replacement row can generally reside in any array within the bank.
In a random access memory device utilizing bank architecture, row redundancy schemes are typically implemented via redundancy circuits, with one redundancy circuit being associated with and being located proximate to each of the memory arrays within the bank. Each redundancy circuit checks incoming addresses intended for its corresponding array against known defective rows of the array and communicates with the other redundancy blocks of the bank to redirect the addresses to predetermined replacement rows within the bank when access of a defective row is requested. While such a scheme is effectively provides row redundancy to the memory device, providing a redundancy circuit at each array can consume a large amount of integrated circuit area.
Memory devices with bank architecture also generally employ a row control circuit at each array for generating timing signals associated with row operations. Each row control circuit, in response to receiving a global row operation initiating signal and the address of its associated array, locally generates all timing signals and related delays necessary for performing a row operation in the associated array. While such a scheme is effectively generates the necessary timing signal to carry-out row operations, generating all timing signals with a row control circuit at each array can also consume a large amount of integrated circuit area. Also, adjustments in delays between timing signals can be cumbersome and time consuming, as such adjustments must be made in the row control circuit at each array.